As a conventional semiconductor device, a semiconductor device will be described below in which four memory macros each having an n-bit test output terminal are mounted. In the description below, by way of example, the memory macros are individually tested by means of direct memory access (DMA).
FIG. 15 is a block diagram showing the configuration of an essential part of a semiconductor device in a conventional example 1 (testing is performed on each memory macro). As shown in FIG. 15, memory macros 1501 to 1504 are provided. First, to test the memory macro 1501, a tester 1509 inputs a test input signal TDIi (i=1 to n; here, n=8) to the memory macro 1501 or all the memory macros 1501 to 1504 through a pad 1510.
During a write operation set by the tester 1509, the memory macro 1501 receives the test input signal TDIi (i=1 to 8), which is written to each memory cell in the memory macro 1501. During a read operation set by the tester, data is read from the memory cells, and a test output signal TDO1i (i=1 to 8) is output from the memory macro 1501.
The test output signal TDO1i is output to the tester 1509 through a selector 1511 and a pad 1512, and compared, in the tester 1509, with an expected value that is a comparison reference value. On the basis of the result of the comparison, the tester 1509 makes a PASS/FAIL determination. The above-described operation is also performed on the memory macros 1502 to 1508.
In the above-described case, the testing is performed on each memory macro, and the time required for the testing thus increases with the number of memory macros. To solve this problem, a proposal has been made of a method of simultaneously testing a plurality of memory macros, which corresponds to a conventional example 2 (see, for example, Japanese Patent Laid-Open No. 2000-133000).
FIG. 16 is a block diagram showing the configuration of an essential part of a semiconductor device in conventional example 2 (a plurality of memory macros are simultaneously tested). In this semiconductor device, as shown in FIG. 16, four outputs TDO1i to TDO4i (i=1 to 8) are simultaneously output by the memory macros and passed through an output synthesizing circuit (AND circuit) 1601. The output synthesizing circuit 1601 subjects the outputs to data compression to output a resulting test output signal CTDOi (i=1 to 8).
Even if any macro contains different data, this cannot be determined simply by compressing the data as described above. Thus, a comparator is used to determine whether or not the signals TDO1i to TDO4i (i=1 to 8) match to output a new PASS/FAIL signal. This one bit and n bits, that is, the n+1 bits, are used to simultaneously test the plurality of macros.
However, such a testing method of a semiconductor device as shown in the conventional example 2, described above, performs the testing with the n+1 bits, increasing the number of terminals required for the testing compared to that in the conventional example 1.
Furthermore, the data from the memory macros are compressed by the output synthesizing circuit 1601. This makes it impossible to determine which of the memory macros is defective. To determine which of the memory macros is defective, it is necessary to retest all the macros. This requires extra testing steps compared to the conventional example 1, increasing the time required to test all the macros.
Moreover, the simultaneous macro testing uses the expected value which corresponds to the comparison reference value and which is different from that used for the individual macro testing. Different test files are thus required for the expected value for the individual macro testing and for the expected value for the simultaneous macro testing. Thus, the conventional example 2 requires much time and effort to appropriately manage and use the test file required to distinguish the conventional example 2 from the conventional example 1.